Split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. The memory cell is shown in FIG. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the drain region 16. A control gate 22 has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 22b that extends up and over the floating gate 20. The floating gate 20 and control gate 22 are insulated from the substrate 12 by a gate oxide 26.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation 24 from the floating gate 20 to the control gate 22 via Fowler-Nordheim tunneling.
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate 22, and a positive voltage on the drain 16. Electron current will flow from the source 14 towards the drain 16. The electrons will accelerate and become heated when they reach the gap between the control gate 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
The memory cell is read by placing positive read voltages on the drain 16 and control gate 22 (which turns on the channel region under the control gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the drain 16), then the portion of the channel region under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state. Those skilled in the art understand that the source and drain can be interchangeable, where the floating gate can extend partially over the source instead of the drain, as shown in FIG. 2.
Split gate memory cells having more than two gates are also known. For example, U.S. Pat. No. 8,711,636 (“the '636 patent”) discloses a memory cells with an additional coupling gate disposed over and insulated from the source region, for better capacitive coupling to the floating gate. See for example FIG. 3 showing coupling gate 24 disposed over source region 14.
A four gate memory disclosed in U.S. Pat. No. 6,747,310 (“the '310 patent”). For example, as shown in FIG. 4, the memory cells have source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 28 over a second portion of the channel region 18, a control gate 22 over the floating gate 20, and an erase gate 30 over the source region 14. Programming is shown by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is shown by electrons tunneling from the floating gate 20 to the erase gate 30.
The memory cells of FIGS. 1 and 2 have been successfully used as flash memory for several technology nodes. It is relatively easy to implement with a low cost process and good performance. One drawback is that the cell size is large and therefore can be competitive for advanced technology nodes. The memory cell of FIG. 4 has been successfully used as embedded flash for several advanced technology nodes. It has very good quality and a competitive cell size. However, the process cost is higher and more complicated than that of the cells in FIGS. 1 and 2. The memory cells of FIG. 3 are less complex than those of FIG. 4 because they have one less gate in each cell. But, conventional manufacturing techniques are still too complex and do not fully enable scaling down the memory cell size.